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Isolated 15-bit A/D Converter Technical Data
HCPL-7860 HCPL-0870, -7870
Features
* 12-bit Linearity * 700 ns Conversion Time (Pre-Trigger Mode 2) * 5 Conversion Modes for Resolution/Speed Trade-Off; 12-bit Effective Resolution with 18 s Signal Delay (14-bit with 94 s) * Fast 3 s Over-Range Detection * Serial I/O (SPI(R), QSPI(R) and Microwire(R) Compatible) * 200 mV Input Range with Single 5 V Supply * 1% Internal Reference Voltage Matching * Offset Calibration * -40C to +85C Operating Temperature Range * 15 kV/s Isolation Transient Immunity * Regulatory Approvals; UL, CSA, VDE
DIGITAL CURRENT SENSOR
+ ISOLATION BOUNDARY +
OUTPUT DATA
INPUT CURRENT
ISOLATED MODULATOR
DIGITAL INTERFACE IC
Hewlett-Packard's Isolated A/D Converter delivers the reliability, small size, superior isolation and over-temperature performance motor drive designers need to accurately measure current at half the price of traditional solutions.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
SPI and QSPI are trademarks of Motorola Corp. Microwire is a trademark of National Semiconductor Inc.
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MICRO-CONTROLLER
HP7860 YYWW
HPx870 YYWW
5965-5255E
Digital Current Sensing Circuit
As shown in Figure 1, using the Isolated 2-chip A/D converter to sense current can be as simple as connecting a current-sensing resistor, or shunt, to the input and reading output data through the 3-wire serial output interface. By choosing the appropriate
shunt resistance, any range of current can be monitored, from less than 1 A to more than 100 A. Even better performance can be achieved by fully utilizing the more advanced features of the Isolated A/D converter, such as the pre-trigger circuit which can reduce conversion time to less
than 1 s, the fast over-range detector for quickly detecting short circuits, different conversion modes giving various resolution/ speed trade-offs, offset calibration mode to eliminate initial offset from measurements, and an adjustable threshold detector for detecting non-short circuit overload conditions.
NON-ISOLATED +5V
ISOLATED +5V + INPUT CURRENT R SHUNT 0.02
VDD1 VIN+ VDD2 MCLK MDAT GND2
CCLK CLAT CDAT MCLK1 MDAT1 MCLK2 MDAT2 GND
VDD CHAN SCLK SDAT CS THR1 OVR1 RESET 3-WIRE SERIAL INTERFACE
C1 0.1 F
VINGND1
C2 0.1 F
+ C3 10 F
HCPL-7860
HCPL-x870
Figure 1: Typical Application Circuit.
Product Overview
Description The HCPL-7860 Isolated Modulator and the HCPL-x870 Digital Interface IC together form an isolated programmable two-chip analog-to-digital converter. The isolated modulator allows direct measurement of motor phase currents in power inverters while the digital interface IC can be programmed to optimize the conversion speed and resolution trade-off. In operation, the HCPL-7860 Isolated Modulator (optocoupler with 3750 VRMS dielectric withstand voltage rating) converts a
low-bandwidth analog input into a high-speed one-bit data stream by means of a sigma-delta () oversampling modulator. This modulation provides for high noise margins and excellent immunity against isolation-mode transients. The modulator data and on-chip sampling clock are encoded and transmitted across the isolation boundary where they are recovered and decoded into separate high-speed clock and data channels. The Digital Interface IC converts the single-bit data stream from the Isolated Modulator into fifteen-bit output words and provides a serial output interface
that is compatible with SPI(R), QSPI(R), and Microwire(R) protocols, allowing direct connection to a microcontroller. The Digital Interface IC is available in two package styles: the HCPL-7870 is in a 16-pin DIP package and the HCPL-0870 is in a 300-mil wide SO-16 surface-mount package. Features of the Digital Interface IC include five different conversion modes, three different pretrigger modes, offset calibration, fast over-range detection, and adjustable threshold detection. Programmable features are configured via the Serial Configuration port. A second multiplexed input is available to allow measurements with a second
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isolated modulator without additional hardware. Because the two inputs are multiplexed, only one conversion at a time can be made and not all features are available for the second channel. The available features for both channels are shown in the table at right.
HCPL-x870 Digital Interface IC
Feature Conversion Mode Offset Calibration Pre-Trigger Mode Over-Range Detection Adjustable Threshold Detection Channel #1 Channel #2
Functional Diagrams
ISOLATION BOUNDARY
CCLK CLAT 1 2 3 4
CH1 CONFIG. INTERFACE CONVERSION INTERFACE
16 VDD 15 CHAN
VDD1 VIN+ VIN- GND1
1 2 3 4
8 7
DECODE
VDD2 MCLK MDAT GND2
CDAT MCLK1 MDAT1
14 SCLK 13 SDAT
12 CS
SIGMADELTA MOD./ ENCODE
5 6 7 8
CH2 THRESHOLD DETECT & RESET
6
5
MCLK2 MDAT2
11 THR1
10 OVR1 9
RESET
SHIELD
GND
HCPL-7860 Isolated Modulator
HCPL-x870 Digital Interface IC
Pin Description, Isolated Modulator
Symbol VDD1 VIN+ VIN- GND1 Description Supply voltage input (4.5 V to 5.5 V) Positive input ( 200 mV recommended) Negative input (normally connected to GND1) Input ground Symbol VDD2 MCLK MDAT GND2 Description Supply voltage input (4.5 V to 5.5 V) Clock output (10 MHz typical) Serial data output Output ground
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Pin Description, Digital Interface IC
Symbol Description CCLK Clock input for the Serial Configuration Interface (SCI). Serial Configuration data is clocked in on the rising edge of CCLK. CLAT Latch input for the Serial Configuration Interface (SCI). The last 8 data bits clocked in on CDAT by CCLK are latched into the appropriate configuration register on the rising edge of CLAT. CDAT Data input for the Serial Configuration Interface (SCI). Serial configuration data is clocked in MSB first. MCLK1 Channel 1 Isolated Modulator clock input. Input Data on MDAT1 is clocked in on the rising edge of MCLK1. Symbol Description VDD Supply voltage (4.5 V to 5.5 V).
CHAN
Channel select input. The input level on CHAN determines which channel of data is used during the next conversion cycle. An input low selects channel 1, a high selects channel 2. Serial clock input. Serial data is clocked out of SDAT on the falling edge of SCLK. Serial data output. SDAT changes from high impedance to a logic low output at the start of a conversion cycle. SDAT then goes high to indicate that data is ready to be clocked out. SDAT returns to a high-impedance state after all data has been clocked out and CS has been brought high. Conversion start input. Conversion begins on the falling edge of CS. CS should remain low during the entire conversion cycle and then be brought high to conclude the cycle. Continuous, programmable-threshold detection for channel 1 input data. A high level output on THR1 indicates that the magnitude of the channel 1 input signal is beyond a user programmable threshold level between 160 mV and 310 mV. This signal continuously monitors channel 1 independent of the channel select (CHAN) signal. High speed continuous over-range detection for channel 1 input data. A high level output on OVR1 indicates that the magnitude of the channel 1 input is beyond full-scale. This signal continuously monitors channel 1 independent of the CHAN signal. Master reset input. A logic high input for at least 100 ns asynchronously resets all configuration registers to their default values and zeroes the Offset Calibration registers.
SCLK
SDAT
MDAT1
Channel 1 Isolated Modulator data input.
CS
MCLK2
Channel 2 Isolated Modulator clock input. Input Data on MDAT2 is clocked in on the rising edge of MCLK2.
THR1
MDAT2
Channel 2 Isolated Modulator data input.
OVR1
GND
Digital ground.
RESET
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Isolated A/D Converter Performance
Electrical Specifications
Unless otherwise noted, all specifications are at VIN+ = -200 mV to +200 mV and VIN- = 0 V; all Typical specifications are at TA = 25C and VDD1 = VDD2 = VDD = 5 V; all Minimum/Maximum specifications are at TA = -40C to +85C, VDD1 = VDD2 = VDD = 4.5 to 5.5 V. Parameter Resolution Integral Nonlinearity Symbol Min. 15 INL 6 0.025 1 4 0.7 326 30 0.14 1 2.5 Typ. Max. Units bits LSB % LSB mV V/ C mV/V mV % % ppm/C % mV Test Conditions Fig. Note 1 2 3 VIN+ = 0 V 5 4
STATIC CONVERTER CHARACTERISTICS
3 4
Differential Nonlinearity DNL Uncalibrated Input Offset VOS -1 Offset Drift vs. Temperature dVOS/dTA Offset drift vs. VDD1 dVOS/dVDD1 Internal Reference Voltage VREF Absolute Reference Voltage -4 Tolerance Reference Voltage -1 Matching VREF Drift vs. Temperature dVREF /dTA VREF Drift vs. VDD1 dVREF /dVDD1 Full Scale Input Range -VREF Recommended Input -200 Voltage Range
4 1 190 0.9 +VREF +200
6 TA = 25C. See Note 5
5
6
DYNAMIC CONVERTER CHARACTERISTICS (Digital Interface IC is set to Conversion Mode 3.)
Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-(Noise + Distortion) Effective Number of Bits Conversion Time SNR THD SND ENOB tC2 tC1 tC0 tDSIG tOVR1 tTHR1 BW CMR 62 73 -67 66 12 0.7 18 37 18 2.7 10 22 20 dB VIN+ = 35 Hz, 400 mVpk-pk (141 mVrms) sine wave. 2,9
10
Signal Delay Over-Range Detect Time Threshold Detect Time Signal Bandwidth Isolation Transient Immunity
2.0 18 15
1.0 22 44 22 4.2
bits s
8 Pre-Trigger Mode 2 7, Pre-Trigger Mode 1 14 Pre-Trigger Mode 0 10 VIN+ = 0 to 400 mV 12 step waveform 11 VISO = 1 kV
7 8
kHz kV/s
9 10 11 12 13
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Notes: 1. Resolution is defined as the total number of output bits. The useable accuracy of any A/D converter is a function of its linearity and signal-tonoise ratio, rather than how many total bits it has. 2. Integral nonlinearity is defined as one-half the peak-to-peak deviation of the best-fit line through the transfer curve for VIN+ = -200 mV to +200 mV, expressed either as the number of LSBs or as a percent of measured input range (400 mV). 3. Differential nonlinearity is defined as the deviation of the actual difference from the ideal difference between midpoints of successive output codes, expressed in LSBs. 4. Data sheet value is the average magnitude of the difference in offset voltage from TA = 25C to TA = -40C, expressed in microvolts per C. 5. All units within each HCPL-7860 standard packaging increment (either 50 per tube or 1000 per reel) have an Absolute Reference Voltage tolerance of 1%. An Absolute Reference Voltage tolerance of 4% is guaranteed between standard packaging increments. 6. Beyond the full-scale input range the output is either all zeroes or all ones. 7. The effective number of bits (or effective resolution) is defined by the
equation ENOB = (SNR-1.76)/6.02 and represents the resolution of an ideal, quantization-noise limited A/D converter with the same SNR. 8. Conversion time is defined as the time from when the convert start signal CS is brought low to when SDAT goes high, indicating that output data is ready to be clocked out. This can be as small as a few cycles of the isolated modulator clock and is determined by the frequency of the isolated modulator clock and the selected Conversion and Pre-Trigger modes. For determining the true signal delay characteristics of the A/D converter for closed-loop phase margin calculations, the signal delay specification should be used. 9. Signal delay is defined as the effective delay of the input signal through the Isolated A/D converter. It can be measured by applying a -200 mV to 200 mV step at the input of modulator and adjusting the relative delay of the convert start signal CS so that the output of the converter is at midscale. The signal delay is the elapsed time from when the step signal is applied at the input to when output data is ready at the end of the conversion cycle. The signal delay is the most important specification for determining the true signal delay characteristics of the A/D converter
10.
11.
12.
13.
and should be used for determining phase margins in closed-loop applications. The signal delay is determined by the frequency of the modulator clock and which Conversion Mode is selected, and is independent of the selected Pre-Trigger Mode and, therefore, conversion time. The minimum and maximum overrange detection time is determined by the frequency of the channel 1 isolated modulator clock. The minimum and maximum threshold detection time is determined by the user-defined configuration of the adjustable threshold detection circuit and the frequency of the channel 1 isolated modulator clock. See the Applications Information section for further detail. The specified times apply for the default configuration. The signal bandwidth is the frequency at which the magnitude of the output signal has decreased 3 dB below its low-frequency value. The signal bandwidth is determined by the frequency of the modulator clock and the selected Conversion Mode. The isolation transient immunity (also known as Common-Mode Rejection) specifies the minimum rate-of-rise of an isolation-mode signal applied across the isolation boundary beyond which the modulator clock or data signals are corrupted.
75.0 VDD1 = 4.5 V VDD1 = 5.0 V VDD1 = 5.5 V
16 14 12
INL - LSB
0.08
74.5
VDD1 = 4.5 V VDD1 = 5.0 V VDD1 = 5.5 V
INL - %
0.07 0.06 0.05 0.04 0.03 0.02 0.01
VDD1 = 4.5 V VDD1 = 5.0 V VDD1 = 5.5 V
74.0
10 8 6 4
SNR
73.5 73.0
2
72.5 -40 -20 0 20 40 60 85
0 -40
-20
0
20
40
60
85
0 -40
-20
0
20
40
60
85
TEMPERATURE - C
TEMPERATURE - C
TEMPERATURE - C
Figure 2. SNR vs. Temperature.
Figure 3. INL (Bits) vs. Temperature.
Figure 4. INL (%) vs. Temperature.
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400 300 VDD1 = 4.5 V VDD1 = 5.0 V VDD1 = 5.5 V
2.5 2.0 VREF CHANGE - % 1.5 1.0 0.5 0 -0.5 -1.0
-20 0 20 40 60 85
200 180
CONVERSION TIME - s
VDD1 = 4.5 V VDD1 = 5.0 V VDD1 = 5.5 V
OFFSET CHANGE - V
200 100 0 -100 -200 -300 -400 -500 -600 -40
160 140 120 100 80 60 40 20 0
PRE-TRIGGER MODE 0 PRE-TRIGGER MODE 1 PRE-TRIGGER MODE 2
-1.5 -40
-20
0
20
40
60
85
1
2
3
4
5
TEMPERATURE - C
TEMPERATURE - C
CONVERSION MODE #
Figure 5. Offset Change vs. Temperature.
Figure 6. VREF Change vs. Temperature.
Figure 7. Conversion Time vs. Conversion Mode.
14
EFFECTIVE RESOLUTION (# BITS)
85 80 75
100 90 80
SIGNAL DELAY - s
1 2 3 4 5
13 12 11 10 9 8
SNR
70 60 50 40 30 20 10 0 1 2 3 4 5
70 65 60 55
1
2
3
4
5
50
CONVERSION MODE #
CONVERSION MODE #
CONVERSION MODE #
Figure 8. Effective Resolution vs. Conversion Mode.
Figure 9. SNR vs. Conversion Mode.
Figure 10. Signal Delay vs. Conversion Mode.
100 90 SIGNAL BANDWIDTH - kHz 80 70 60 50 40 30 20 10 0 1 2 3 4 5
2 s/DIV. OVR1 (200 mV/DIV.) THR1 (2 V/DIV.) VIN+ (200 mV/DIV.)
CONVERSION MODE #
Figure 11. Signal Bandwidth vs. Conversion Mode.
Figure 12. Over-Range and Threshold Detect Times.
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Isolated Modulator
Ordering Information Specify Part Number followed by Option Number (if desired). Example: HCPL-7860#XXX No Option = Standard DIP package, 50 per tube. 300 = Gull Wing Surface Mount Option, 50 per tube. 500 = Tape and Reel Packaging Option, 1000 per reel. Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.
Package Outline Drawings
8-pin DIP Package
9.40 (0.370) 9.90 (0.390) 8 7 6 5 REFERENCE VOLTAGE MATCHING SUFFIX* DATE CODE 6.10 (0.240) 6.60 (0.260) 7.36 (0.290) 7.88 (0.310)
TYPE NUMBER
0.18 (0.007) 0.33 (0.013)
HP 7860X YYWW PIN ONE 1.19 (0.047) MAX. 1 2 3 4
5 TYP.
1.78 (0.070) MAX.
4.70 (0.185) MAX. PIN ONE 0.51 (0.020) MIN. 2.92 (0.115) MIN. 1 2 3 0.76 (0.030) 1.24 (0.049) 0.65 (0.025) MAX. 2.28 (0.090) 2.80 (0.110) DIMENSIONS IN MILLIMETERS AND (INCHES). 4
PIN DIAGRAM VDD1 VIN+ VIN- VDD2 8 MCLK 7 MDAT 6
GND1 GND2 5
*ALL UNITS WITHIN EACH HCPL-7860 STANDARD PACKAGING INCREMENT (EITHER 50 PER TUBE OR 1000 PER REEL) HAVE A COMMON MARKING SUFFIX TO REPRESENT AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF 1%. AN ABSOLUTE REFERENCE VOLTAGE TOLERANCE OF 4% IS GUARANTEED BETWEEN STANDARD PACKAGING INCREMENTS.
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8-pin DIP Gull Wing Surface Mount Option 300
PIN LOCATION (FOR REFERENCE ONLY) 9.65 0.25 (0.380 0.010)
8 7 6 5
1.02 (0.040) 1.19 (0.047)
4.83 TYP. (0.190) 6.350 0.25 (0.250 0.010) 9.65 0.25 (0.380 0.010)
MOLDED
1
2
3
4
1.19 (0.047) 1.78 (0.070) 1.780 (0.070) MAX. 9.65 0.25 (0.380 0.010) 7.62 0.25 (0.300 0.010)
0.380 (0.015) 0.635 (0.025)
1.19 (0.047) MAX.
4.19 MAX. (0.165)
0.255 (0.075) 0.010 (0.003)
1.080 0.320 (0.043 0.013) 2.540 (0.100) BSC
0.51 0.130 (0.020 0.005)
0.635 0.25 (0.025 0.010) 12 NOM.
DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005
LEAD COPLANARITY MAXIMUM: 0.102 (0.004)
Package Characteristics
Unless otherwise noted, all specifications are at TA = +25C. Parameter Input-Output Momentary Withstand Voltage (See note ** below) Resistance (Input - Output) Capacitance (Input - Output) Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance Symbol Min. VISO 3750 Typ. Max. Units Vrms pF C/W C/W Test Conditions RH 50%, t = 1 min. Note 14,15
RI-O CI-O jci jco
1012 1011
1013 0.7 96 114
VI-O = 500 Vdc TA = 100C f = 1 MHz Thermocouple located at center underside of package
15
** The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note 1074, Optocoupler Input-Output Endurance Voltage.
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Maximum Solder Reflow Thermal Profile
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 1 T = 100C, 1.5C/SEC
T = 145C, 1C/SEC T = 115C, 0.3C/SEC
TEMPERATURE - C
2
3
4
5
6
7
8
9
10
11
12
TIME - MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
Regulatory Information
The HCPL-7860 (isolated modulator) has been approved by the following organizations: UL Recognized under UL 1577, Component Recognition Program, File E55361. VDE (Pending) Approved under VDE 0884/06.92 with VIORM = 848 VPEAK. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324.
VDE 0884 Insulation Characteristics
Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 300 Vrms for rated mains voltage 600 Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial Discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec) Safety-Limiting Values-Maximum Values Allowed in the Event of a Failure, also see Figure 13. Case Temperature Input Power Output Power Insulation Resistance at TSI, VIO = 500 V Symbol Characteristic I - IV I - III 40/85/21 2 848 1590 Unit
VIORM VPR
V PEAK V PEAK
VPR
1273
V PEAK
VIOTM
6000
V PEAK C mW mW
TS IS, INPUT PS, OUTPUT RS
175 80 250 109
*Refer to the optocoupler section of the Optoelectronics Designer's Catalog, under Product Safety Regulations section, (VDE 0884) for a detailed description of Method a and Method b partial discharge test profiles. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
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300 250
PSi - POWER - mW
PSi, OUTPUT 200 150 100 50 0 MAX. OPERATING TEMP. IS 100 C PSi, INPUT
0
50
100
150
200
TA - TEMPERATURE - C
Figure 13. Dependence of SafetyLimiting Values on Temperature.
Insulation and Safety Related Specifications
Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol Value Units L(I01) 7.4 mm L(I02) 8.0 0.5 mm mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
175 IIIa
Volts
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter Storage Temperature Ambient Operating Temperature Supply Voltages Steady-State Input Voltage Two Second Transient Input Voltage Output Voltages Lead Solder Temperature Solder Reflow Temperature Profile Min. Max. Units Note -55 125 C -40 +85 C 0 5.5 Volts -2.0 VDD1 + 0.5 Volts 16 -6.0 MCLK, MDAT -0.5 VDD2 +0.5 Volts 260C for 10 sec., 1.6 mm below seating plane 17 See Maximum Solder Reflow Thermal Profile section Symbol TS TA VDD1, VDD2 VIN+, VIN-
Recommended Operating Conditions
Parameter Ambient Operating Temperature Supply Voltages Input Voltage Symbol TA VDD1, VDD2 VIN+, VINMin. -40 4.5 -200 Max. +85 5.5 +200 Units C V mV Note
16
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Electrical Specifications, Isolated Modulator
Unless otherwise noted, all specifications are at VIN+ = 0 V and VIN- = 0 V, all Typical specifications are at TA = 25C and VDD1 = VDD2 = 5 V, and all Minimum and Maximum specifications apply over the following ranges: TA = -40C to +85C, VDD1 = 4.5 to 5.5 V and VDD2 = 4.5 to 5.5 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Average Input Bias Current IIN -1.0 A 14 18 Average Input Resistance RIN 270 k Input DC Common-Mode CMRRIN 55 dB 19 Rejection Ratio Output Logic High Voltage VOH 3.9 4.9 V IOUT = -100 A Output Logic Low Voltage VOL 0.3 0.6 V IOUT = 1.6 mA Output Short Circuit Current |IOSC| 10 mA VOUT = VDD2 or GND2 20 Input Supply Current IDD1 9.5 15 mA VIN+ = -350 mV 15 Output Supply Current IDD2 8.8 15 mA to +350 mV 16 Output Clock Frequency fCLK 9 11 14 MHz 17 Data Hold Time tHDDAT 15 ns 21
Notes: 14. In accordance with UL1577, for devices with minimum VISO specified at 3750 Vrms, each isolated modulator (optocoupler) is proof-tested by applying an insulation test voltage greater than 4500 Vrms for one second (leakage current detection limit II-O < 5 a). This test is performed before the Method b, 100% production test for partial discharge shown in VDE 0884 Insulation Characteristics Table. 15. This is a two-terminal measurement: pins 1-4 are shorted together and pins 5-8 are shorted together. 16. If VIN- (pin 3) is brought above VDD1 - 2 V with respect to GND1 an internal optical-coupling test mode may be activated. This test mode is not intended for customer use. 17. HP recommends the use of non-chlorinated solder fluxes. 18. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown. 19. CMRRIN is defined as the ratio of the gain for differential inputs applied between VIN+ and VIN- to the gain for common-mode inputs applied to both VIN+ and VIN- with respect to input ground GND1. 20. Short-circuit current is the amount of output current generated when either output is shorted to VDD2 or GND2. Use under these conditions is not recommended. 21. Data hold time is amount of time that the data output MDAT will stay stable following the rising edge of output clock MCLK.
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1 0 -1 -2
IDD1 - mA
10.5 -40 C 25 C 85 C
10.0
IIN - mA
-3 -4 -5 -6 -7 -8 -9 -6 -4 -2 0 VIN - V 2 4 6
9.5
9.0
8.5
8.0 -400
-200
0 VIN - mV
200
400
Figure 14. IIN vs. VIN.
Figure 15. IDD1 vs. VIN.
9.4
CLOCK FREQUENCY - MHz
11.05
9.2 9.0
IDD2 - mA
11.00
8.8 8.6 8.4 8.2 8.0 -400 -200 -40 C 25 C 85 C 0 VIN - mV 200 400
10.95
10.90 VDD1 = 4.5 V VDD1 = 5.0 V VDD1 = 5.5 V -20 0 20 40 60 85
10.85
10.80 -40
TEMPERATURE - C
Figure 16. IDD2 vs. VIN.
Figure 17. Clock Frequency vs. Temperature.
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Digital Interface IC
Ordering Information Specify Part Number followed by Option Number (if desired). Example HCPL-7870 HCPL-0870#XXX No Option = Standard 16-pin SO package, 47 per tube. 500 = Tape and Reel Packaging Option, 1000 per reel. Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor. Standard 16-pin DIP package, 25 per tube.
Package Outline Drawings
Standard 16-pin DIP Package
16
15
14
13
12
11
10
9 TYPE NUMBER DATE CODE
R 0.030 x 0.030 DP HP 7870 YYWW
1
2
3
4
5
6
7
8
0.310 0.010 (OUTER TO OUTER) 0.754 7 7 0.150 0.010 0.060 0.060 0.260 0.010 0.002 0.018 0.003 0.100 0.010 DIMENSIONS IN INCHES. TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.002 0.258
0.130
0.130 0.010
0.060
0.310/0.380 (CENTER TO CENTER)
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Standard 16-pin SO Package
TOP VIEW PIN NO. 1 IDENTIFIER 1.27 (0.050) x 0.075 (0.003) DEPTH SHINY SURFACE 16 15 14 13 12 11 10 9 1.90 (0.075)
BOTTOM VIEW 1.90 (0.075)
0.33 x 45 (0.013 x 45)
1.27 (0.050) x 0.075 (0.003) DEPTH (2x) EJECTOR PIN SHINY SURFACE
7.544 0.05 (0.297 0.002)
HP 0870 YYWW
10.00-10.65 (0.394-0.419) (TIP TO TIP)
TH
XX
1.27 (0.050)
1
2
3
4
5
6
7
8
1.27 (0.050) SIDE VIEW 1.016 0.025 (0.040 0.001) 7 2.286 (0.090) 1.27 BSC 0.33-0.51 (0.050 BSC) (0.013-0.020) R 0.18 (R 0.007) ALL CORNERS AND EDGES 0.10-0.30 (0.004-0.0118) PARTING LINE 0.01 (0.004) SEATING PLANE 10.21 0.10 (0.402 0.002) 2.386-2.586 (0.094-0.1018) A 0.23-0.32 (0.0091-0.0125) 1.016 REF. (0.040) DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.010 xx.xxx = 0.002 0 - 8 0.40 - 1.27 (0.016 - 0.050) DETAIL A END VIEW
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Maximum Solder Reflow Thermal Profile
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 T = 145C, 1C/SEC T = 115C, 0.3C/SEC
TEMPERATURE - C
T = 100C, 1.5C/SEC
1
2
3
4
5
6
7
8
9
10
11
12
TIME - MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
Absolute Maximum Ratings
Parameter Storage Temperature Ambient Operating Temperature Supply Voltage Input Voltage Output Voltage Lead Solder Temperature Solder Reflow Temperature Profile Symbol Min. Max. Units TS -55 +125 C TA -40 +85 C VDD 0 5.5 V All Inputs -0.5 VDD + 0.5 V All Outputs -0.5 VDD + 0.5 V 260C for 10 seconds, 1.6 mm below seating plane See Reflow Thermal Profile Note
17
Note: 17. HP recommends the use of non-chlorinated solder fluxes.
Recommended Operating Conditions
Parameter Ambient Operating Temperature Supply Voltage Input Voltage Symbol TA VDD All Inputs Min. -40 4.5 0 Max. +85 5.5 VDD Units C V V Note
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Electrical Specifications, Digital Interface IC
Unless otherwise noted, all Typical specifications are at TA = 25C and VDD = 5 V, and all Minimum and Maximum specifications apply over the following ranges: TA = -40C to +85C and VDD = 4.5 to 5.5 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Supply Current IDD 20 35 mA fCLK = 10 MHz DC Input Current IIN 0.001 10 A Input Logic Low Voltage VIL 0.8 V Input Logic High Voltage VIH 2.0 V Output Logic Low Voltage VOL 0.15 0.4 V IOUT = 4 mA Output Logic High Voltage VOH 4.3 5.0 V IOUT = -400 A Clock Frequency (CCLK, fCLK 20 MHz MCLK and SCLK) Clock Period (CCLK, tPER 50 ns 18, MCLK and SCLK) 19 Clock High Level Pulse tPWH 20 ns Width (CCLK, MCLK and SCLK) Clock Low Level Pulse tPWL 20 Width (CCLK, MCLK and SCLK) Setup Time from DAT to tSUCLK 10 18 Rising Edge of CLK (CDAT, CCLK, MDAT and MCLK) DAT Hold Time after tHDCLK 10 Rising Edge of CLK (CDAT, CCLK, MDAT and MCLK) Setup Time from Falling tSUCL1 20 Edge of CLAT to First Rising Edge of CCLK Setup Time from Last tSUCL2 20 Rising Edge of CCLK to Rising Edge of CLAT Delay Time from Falling tDSDAT 15 19 Edge of SCLK to SDAT Setup Time from Data tSUS 200 Ready to First Falling Edge of SCLK Setup Time from CHAN tSUCHS 20 to falling edge of CS Reset High Level Pulse tPWR 100 Width
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tSUCL1 CLAT
tSUCL2
CDAT
B7
B6 tHDCLK
B5
B4
B3
B2
B1
B0
tSUCLK
tPWH CCLK tPER
tPWL
Figure 18. Serial Configuration Interface Timing.
CHAN
tSUCHS
CS
SDAT
B14
B13
B12
B11
B10
B1
B0
tDSDAT
tPWH 4 5 6 tPER 15 16
SCLK
1
2
3
tC
tSUS
tPWL
Figure 19. Conversion Timing.
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Applications Information
Product Description
The HCPL-7860 Isolated Modulator (optocoupler) uses sigmadelta modulation to convert an analog input signal into a highspeed (10 MHz) single-bit digital data stream; the time average of the modulator's single-bit data is directly proportional to the input signal. The isolated modulator's other main function is to provide galvanic isolation between the analog input and the digital output. An internal voltage reference determines the fullscale analog input range of the modulator (approximately 320 mV); an input range of 200 mV is recommended to achieve optimal performance.
The primary functions of the HCPL-x870 Digital Interface IC are to derive a multi-bit output signal by averaging the single-bit modulator data, as well as to provide a direct microcontroller interface. The effective resolution of the multi-bit output signal is a function of the length of time (measured in modulator clock cycles) over which the average is taken; averaging over longer periods of time results in higher resolution. The Digital Interface IC can be configured for five conversion modes which have different combinations of speed and resolution to achieve the desired level of performance. Other functions of the HCPLx870 Digital Interface IC include a Phase Locked Loop based pretrigger circuit that can either give more precise control of the
effective sampling time or reduce conversion time to less than 1 s, a fast over-range detection circuit that rapidly indicates when the magnitude of the input signal is beyond full-scale, an adjustable threshold detection circuit that indicates when the magnitude of the input signal is above a useradjustable threshold level, an offset calibration circuit, and a second multiplexed input that allows a second Isolated Modulator to be used with a single Digital Interface IC. The digital output format of the Isolated A/D Converter is 15 bits of unsigned binary data. The input full-scale range and code assignment is shown in Table 1 below. Although the output contains 15 bits of data, the effective resolution is lower and is determined by selected conversion mode as shown in Table 2 below.
Table 1. Input Full-Scale Range and Code Assignment.
Analog Input Full Scale Range Minimum Step Size +Full Scale Zero -Full Scale Voltage Input 640 mV 20 V +320 mV 0 mV -320 mV Digital Output 32768 LSBs 1 LSB 111111111111111 100000000000000 000000000000000
Table 2. Isolated A/D Converter Typical Performance Characteristics.
Conversion Mode 1 2 3 4 5 Signal-toNoise Ratio (dB) 83 79 73 66 53 Effective Resolution (bits) 13.5 12.8 11.9 10.7 8.5 Conversion Time (s) Pre-Trigger Mode 0 1 2 188 94 95 47 37 18 0.7 19 10 10 5 Signal Delay (s) 94 47 18 10 5 Signal Bandwidth (kHz) 3.4 6.9 22 45 90
Note: Bold italic type indicates Default values.
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Digital Interface Timing
Power Up/Reset
At power up, the digital interface IC should be reset either manually, by bringing the RESET pin (pin 9) high for at least 100 ns, or automatically by connecting a 10 F capacitor between the RESET pin and VDD (pin 16). The RESET pin operates asynchronously and places the IC in its default configuration, as specified in the Digital Interface Configuration section.
impedance state after a few cycles of the Isolated Modulator's clock. The amount of time between the falling edge of CS and the rising edge of SDAT depends on which conversion and pre-trigger modes are selected; it can be as low as 0.7 s when using pre-trigger mode 2, as explained in the Digital Interface Configuration section.
Serial Configuration Timing
The HCPL-x870 Digital Interface IC is programmed using the Serial Configuration Interface (SCI) which consists of the clock (CCLK), data (CDAT), and enable/latch (CLAT) signals. Figure 18 illustrates the timing for the serial configuration interface. To send a byte of configuration data to the HCPL-x870, first bring CLAT low. Then clock in the eight bits of the configuration byte (MSB first) using CDAT and the rising edge of CCLK. After the last bit has been clocked in, bringing CLAT high again will latch the data into the appropriate configuration register inside the interface IC. If more than eight bits are clocked in before CLAT is brought high, only the last eight bits will be used. Refer to the Digital Interface Configuration section to determine appropriate configuration data. If the default configuration of the digital interface IC is acceptable, then CCLK, CDIN and CLAT may be connected to either VDD or GND.
Conversion Timing
Figure 19 illustrates the timing for one complete conversion cycle. A conversion cycle is initiated on the falling edge of the convert start signal (CS); CS should be held low during the entire conversion cycle. When CS is brought low, the serial output data line (SDAT) changes from a high-impedance to the low state, indicating that the converter is busy. A rising edge on SDAT indicates that data is ready to be clocked out. The output data is clocked out on the negative edges of the serial clock pulses (SCLK), MSB first. A total of 16 pulses is needed to clock out all of the data. After the last clock pulse, CS should be brought high again, causing SDAT to return to a highimpedance state, completing the conversion cycle. If the external circuit uses the positive edges of SCLK to clock in the data, then a total of sixteen bits is clocked in, the first bit is always high (indicating that data is ready) followed by 15 data bits. If fewer than 16 cycles of SCLK are input before CS is brought high, the conversion cycle will terminate and SDAT will go to the high-
sion cycle. A logic low level selects channel one, a high level selects channel 2. CHAN should not be changed during a conversion cycle. The state of the CHAN signal has no effect on the behavior of either the over-range detection circuit (OVR1) or the adjustable threshold detection circuit (THR1). Both OVR1 and THR1 continuously monitor channel 1 independent of the CHAN signal. CHAN also does not affect the behavior of the pretrigger circuit, which is tied to the conversion timing of channel 1, as explained in the Digital Interface Configuration section.
Digital Interface Configuration
Configuration Registers
The Digital Interface IC contains four 6-bit configuration registers that control its behavior. The two LSBs of any byte clocked into the serial configuration port (CDAT, CCLK, CLAT) are used as address bits to determine which register the data will be loaded into. Registers 0 and 1 (with address bits 00 and 01) specify the conversion and offset calibration modes of channels 1 and 2, register 2 (address bits 10) specifies the behavior of the adjustable threshold circuit, and register 3 (address bits 11) specifies which pre-trigger mode to use for channel 1. These registers are illustrated in Table 3 below, with default values indicated in bold italic type. Note that there are several reserved bits which should always be set low and that the configuration registers should not be changed during a conversion cycle.
Channel Select Timing
The channel select signal (CHAN) determines which input channel will be used for the next conver-
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Table 3. Register Configuration.
Register 0 Configuration Data Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Channel 1 Conversion Mode Channel 1 Offset Cal High 1 High High Threshold Detection Time High Low Pre-Trigger Mode 3 Low Low Low Low Low Low High High
Note: Bold italic type indicates default values. Reserved bits should be set low.
Bit 2 Reserved
Address Bits Bit 1 Bit 0
High Low Low Channel 2 Conversion Mode
Low Channel 2 Offset Cal
Low Reserved
Low
Low
Low
Low Low Threshold Level
Low
Low
High
2
Low
Low Low Reserved
Low
High
Low
Conversion Mode The conversion mode determines the speed/resolution trade-off for the Isolated A/D converter. The four MSBs of registers 0 and 1
determine the conversion mode for the appropriate channel. The bit settings for choosing a particular conversion mode are shown in Table 4 below. See Table 2 for
a summary of how performance changes as a function of conversion mode setting. Combinations of data bits not specified in Table 4 below are not recommended.
Table 4. Conversion Mode Configuration.
Conversion Mode 1 2 3 4 5 Bit 7 Low Low High High High Configuration Bit 6 High Low High High Low Data Bits Bit 5 Low High High Low High Bit 4 High High Low Low Low
Note: Bold italic type indicates default values.
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Pre-Trigger Mode The pre-trigger mode refers to the operation of a PLL-based circuit that affects the sampling behavior and conversion time of the A/D converter when channel 1 is selected. The PLL pre-trigger circuit has two modes of operation; the first mode allows more precise control of the time at which the analog input voltage is effectively sampled, while the second mode essentially eliminates the time between when the external convert start command is given and when output data is available (reducing it to less than 1 s). A brief description of how the A/D converter works with the pre-trigger circuit disabled will help explain how the pre-trigger circuit affects operation when it is enabled. With the pre-trigger circuit is disabled (pre-trigger mode 0), Figure 20 illustrates the relationship between the convert start command, the weighting function used to average the modulator data, and the data ready signal. The weighted averaging of the modulator data begins immedi-
ately following the convert start command. The weighting function increases for half of the conversion cycle and then decreases back to zero, at which time the data ready signal is given, completing the conversion cycle. The analog signal is effectively sampled at the peak of the weighting function, half-way through the conversion cycle. This is the default mode. If the convert start signal is periodic (i.e., at a fixed frequency) and the PLL pre-trigger circuit is enabled (pre-trigger modes 1 or 2), either the peak of the weighting function or the end of the conversion cycle can be aligned to the external convert start command, as shown in Figure 20. The Digital Interface IC can therefore synchronize the conversion cycle so that either the beginning, the middle, or the end of the conversion is aligned with the external convert start command, depending on whether pre-trigger mode 0, 1, or 2 is selected, respectively. The only requirement is that the convert start signal for channel 1 be
periodic. If the signal is not periodic and pre-trigger mode 1 or 2 is selected, then the pretrigger circuit will not function properly. An important distinction should be made concerning the difference between conversion time and signal delay. As can be seen in Figure 20, the amount of time from the peak of the weighting function (when the input signal is being sampled) to when output data is ready is the same for all three modes. This is the actual delay of the analog signal through the A/D converter and is independent of the "conversion time," which is simply the time between the convert start signal and the data ready signal. Because signal delay is the true measure of how much phase shift the A/D converter adds to the signal, it should be used when making calculations of phase margin and loop stability in feedback systems. There are different reasons for using each of the pre-trigger modes. If the signal is not
WEIGHTING FUNCTION
CONVERT START - CS
DATA READY - SDAT
A) PRE-TRIGGER MODE 0
B) PRE-TRIGGER MODE 1
C) PRE-TRIGGER MODE 2
Figure 20. Pre-Trigger Modes 0, 1, and 2.
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periodic, then the pre-trigger circuit should be disabled by selecting pre-trigger mode 0. If the most time-accurate sampling of the input signal is desired, then mode 1 should be selected. If the shortest possible conversion time is desired, then mode 2 should be selected.
The pre-trigger circuit functions only with channel 1; the circuit ignores any convert start signals while channel 2 is selected with the CHAN input. This allows conversions on channel 2 to be performed between conversions on channel 1 without affecting the operation of the pre-trigger circuit. As long as the convert
start signals are periodic while channel 1 is selected, then the pre-trigger circuit will function properly. The three different pre-trigger modes are selected using bits 6 and 7 of register 3, as shown in Table 5 below.
Table 5. Pre-Trigger Mode Configuration.
Pre-Trigger Mode 0 1 2 Configuration Data Bits Bit 7 Bit 6 Low Low Low High High Don't Care
Note: Bold italic type indicates default values.
Offset Calibration The offset calibration circuit can be used to separately calibrate the offsets of both channels 1 and 2. The offset calibration circuit contains a separate offset register for each channel. After an offset calibration sequence, the offset registers will contain a value equal to the measured offset, which will then be subtracted from all subsequent conversions. A hardware reset (bringing the RESET pin high for at least 100 ns) is required to reset the offset calibration registers to zero. The following sequence is recommended for performing an offset calibration: 1. Select the appropriate channel using the CHAN pin (low = channel 1, high = channel 2). 2. Force zero volts at the input of the selected isolated modulator. 3. Send a configuration data byte to the appropriate register for
the selected channel (register 0 for channel 1, register 1 for channel 2). Bit 3 of the configuration byte should be set high to enable offset calibration mode and bits 4 through 7 should be set to select conversion mode 1 to achieve the highest resolution measurement of the offset. 4. Perform one complete conversion cycle by bringing CS low until SDAT goes high, indicating completion of the conversion cycle. Because bit 3 of the configuration has been set high, the uncalibrated output data from the conversion will be stored in the appropriate offset calibration register and will be subtracted from all subsequent conversions on that channel. If multiple conversion cycles are performed while the offset calibration mode is enabled, the uncalibrated data from the last conversion cycle will be stored in the offset calibration register.
5. Send another configuration byte to the appropriate register for the selected channel, setting bit 3 low to disable calibration mode and setting bits 4 through 7 to select the desired conversion mode for subsequent conversions on that channel. To calibrate both channels, perform the above sequence for each channel. The offset calibration sequence can be performed as often as needed. The table below summarizes how to turn the offset calibration mode on or off using bit 3 of configuration registers 0 and 1.
Table 6. Offset Calibration Configuration.
Offset Calibration Mode Off On Configuration Data Bits Bit 3 Low High
Note: Bold italic type indicates default values.
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Over-Range Detection The over-range detection circuit allows fast detection of when the magnitude of the input signal on channel 1 is near or beyond full scale, causing the OVR1 output to go high. This circuit can be very useful in current-sensing applications for quickly detecting when a short-circuit occurs. The overrange detection circuit works by detecting when the modulator output data has not changed state for at least 25 clock cycles in a row, indicating that the input signal is near or beyond fullscale, positive or negative. Typical response time to overrange signals is less than 3 s. The over-range circuit actually begins to indicate an over-range condition when the magnitude of the input signal exceeds approximately 250 mV; it starts to generate periodic short pulses on OVR1 which get longer and more frequent as the input signal approaches full scale. The OVR1 output stays high continuously when the input is beyond full scale. The over-range detection circuit continuously monitors channel 1 independent of which channel is selected with the CHAN signal. This allows continuous monitoring of channel 1 for faults while converting an input signal on channel 2.
Adjustable Threshold Detection The adjustable threshold detector causes the THR1 output to go high when the magnitude of the input signal on channel 1 exceeds a user-defined threshold level. The threshold level can be set to one of 16 different values between approximately 160 mV and 310 mV. The adjustable threshold detector uses a smaller version of the main conversion circuit in combination with a digital comparator to detect when the magnitude of the input signal on channel 1 is beyond the defined threshold level. As with the main conversion circuit, there is a trade-off between speed and resolution with the threshold detector; selecting faster detection times exhibit more noise as the signal passes through the threshold, while slower detection times offer lower noise. Both the detection time and threshold level
are programmable using bits 2 through 7 of configuration register 2, as shown in Tables 7 and 8 below. As with the over-range detector, the adjustable threshold detector continuously monitors channel 1 independent of which channel is selected with the CHAN signal. This allows continuous monitoring of channel 1 for faults while converting Channel 2.
Table 7. Threshold Detection Configuration.
Threshold Detection Time 2 - 6 s 3 - 10 s 5 - 20 s 10 - 35 s Configuration Data Bits Bit 7 Bit 6 Low Low Low High High Low High High
Note: Bold italic type indicates default values.
Table 8. Threshold Level Configuration.
Threshold Level 160 mV 170 mV 180 mV 190 mV 200 mV 210 mV 220 mV 230 mV 240 mV 250 mV 260 mV 270 mV 280 mV 290 mV 300 mV 310 mV Configuration Data Bits Bit 5 Bit 4 Bit 3 Bit 2 Low Low Low Low Low Low Low High High Low High High Low Low High High Low High High Low Low Low High High Low High High Low Low High High Low High
Note: Bold italic type indicates default values.
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Analog Interfacing
Power Supplies and Bypassing
The recommended application circuit is shown in Figure 21. A floating power supply (which in many applications could be the same supply that is used to drive the high-side power transistor) is regulated to 5 V using a simple zener diode (D1); the value of resistor R1 should be chosen to supply sufficient current from the existing floating supply. The voltage from the current sensing resistor or shunt (Rsense) is applied to the input of the HCPL7860 (U2) through an RC antialiasing filter (R2 and C2). And finally, the output clock and data of the isolated modulator are connected to the digital interface IC. Although the application circuit is relatively simple, a few recommendations should be followed to ensure optimal performance. The power supply for the isolated modulator is most often obtained from the same supply used to power the power transistor gate
FLOATING POSITIVE SUPPLY HV+ GATE DRIVE CIRCUIT
drive circuit. If a dedicated supply is required, in many cases it is possible to add an additional winding on an existing transformer. Otherwise, some sort of simple isolated supply can be used, such as a line powered transformer or a high-frequency DC-DC converter. An inexpensive 78L05 threeterminal regulator can also be used to reduce the floating supply voltage to 5 V. To help attenuate high-frequency power supply noise or ripple, a resistor or inductor can be used in series with the input of the regulator to form a low-pass filter with the regulator's input bypass capacitor. As shown in Figure 21, 0.1 F bypass capacitors (C1 and C3) should be located as close as possible to the input and output power-supply pins of the isolated modulator (U2). The bypass capacitors are required because of the high-speed digital nature of the signals inside the isolated modulator. A 0.01 F bypass
capacitor (C2) is also recommended at the input due to the switched-capacitor nature of the input circuit. The input bypass capacitor also forms part of the anti-aliasing filter, which is recommended to prevent highfrequency noise from aliasing down to lower frequencies and interfering with the input signal.
PC Board Layout
The design of the printed circuit board (PCB) should follow good layout practices, such as keeping bypass capacitors close to the supply pins, keeping output signals away from input signals, the use of ground and power planes, etc. In addition, the layout of the PCB can also affect the isolation transient immunity (CMR) of the isolated modulator, due primarily to stray capacitive coupling between the input and the output circuits. To obtain optimal CMR performance, the layout of the PC board should minimize any stray coupling by maintaining the maximum possible distance between the input and output sides of the circuit and ensuring
+5V
R1 CCLK D1 5.1 V R2 39 MOTOR C1 0.1 F VDD1 VIN+ VIN+ C2 0.01 F GND1 RSENSE VDD2 MCLK MDAT GND2 C3 0.1 F CLAT CDAT MCLK1 MDAT1 MCLK2 MDAT2 GND VDD CHAN SCLK SDAT CS THR1 OVR1 RESET TO CONTROL CIRCUIT
HCPL-7860
HCPL-X870
HV-
Figure 21. Recommended Application Circuit.
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that any ground or power plane on the PC board does not pass directly below or extend much wider than the body of the isolated modulator. Shunt Resistors The current-sensing shunt resistor should have low resistance (to minimize power dissipation), low inductance (to minimize di/dt induced voltage spikes which could adversely affect operation), and reasonable tolerance (to maintain overall circuit accuracy). Choosing a particular value for the shunt is usually a compromise between minimizing power dissipation and maximizing accuracy. Smaller shunt resistances decrease power dissipation, while larger shunt resistances can improve circuit accuracy by utilizing the full input range of the isolated modulator. The first step in selecting a shunt is determining how much current the shunt will be sensing. The graph in Figure 22 shows the RMS current in each phase of a three-phase induction motor as a function of average motor output power (in horsepower, hp) and motor drive supply voltage. The
MOTOR OUTPUT POWER - HORSEPOWER
40 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 35 440 380 220 120
maximum value of the shunt is determined by the current being measured and the maximum recommended input voltage of the isolated modulator. The maximum shunt resistance can be calculated by taking the maximum recommended input voltage and dividing by the peak current that the shunt should see during normal operation. For example, if a motor will have a maximum RMS current of 10 A and can experience up to 50% overloads during normal operation, then the peak current is 21.1 A (=10x1.414x1.5). Assuming a maximum input voltage of 200 mV, the maximum value of shunt resistance in this case would be about 10 m. The maximum average power dissipation in the shunt can also be easily calculated by multiplying the shunt resistance times the square of the maximum RMS current, which is about 1 W in the previous example. If the power dissipation in the shunt is too high, the resistance of the shunt can be decreased below the maximum value to decrease power dissipation. The minimum value of the shunt is limited by precision and accuracy requirements of the design. As the shunt value is reduced, the output voltage across the shunt is also reduced, which means that the offset and noise, which are fixed, become a larger percentage of the signal amplitude. The selected value of the shunt will fall somewhere between the minimum and maximum values, depending on the particular requirements of a specific design. When sensing currents large enough to cause significant heating of the shunt, the
temperature coefficient (tempco) of the shunt can introduce nonlinearity due to the signal dependent temperature rise of the shunt. The effect increases as the shunt-to-ambient thermal resistance increases. This effect can be minimized either by reducing the thermal resistance of the shunt or by using a shunt with a lower tempco. Lowering the thermal resistance can be accomplished by repositioning the shunt on the PC board, by using larger PC board traces to carry away more heat, or by using a heat sink. For a two-terminal shunt, as the value of shunt resistance decreases, the resistance of the leads becomes a significant percentage of the total shunt resistance. This has two primary effects on shunt accuracy. First, the effective resistance of the shunt can become dependent on factors such as how long the leads are, how they are bent, how far they are inserted into the board, and how far solder wicks up the lead during assembly (these issues will be discussed in more detail shortly). Second, the leads are typically made from a material such as copper, which has a much higher tempco than the material from which the resistive element itself is made, resulting in a higher tempco for the shunt overall. Both of these effects are eliminated when a four-terminal shunt is used. A four-terminal shunt has two additional terminals that are Kelvin-connected directly across the resistive element itself; these two terminals are used to monitor the voltage across the resistive element while the other two terminals are used to carry the load current. Because of the Kelvin connection, any voltage
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MOTOR PHASE CURRENT - A (rms)
Figure 22. Motor Output Horsepower vs. Motor Phase Current and Supply Voltage.
drops across the leads carrying the load current should have no impact on the measured voltage. Several four-terminal shunts from Isotek (Isabellenhutte) suitable for sensing currents in motor drives up to 71 Arms (71 hp or 53 kW) are shown in Table 9; the maximum current and motor power range for each of the PBVseries shunts are indicated. For shunt resistances from 50 m down to 10 m, the maximum current is limited by the input voltage range of the isolated modulator. For the 5 m and 2 m shunts, a heat sink may be required due to the increased power dissipation at higher currents. When laying out a PC board for the shunts, a couple of points should be kept in mind. The Kelvin connections to the shunt should be brought together under the body of the shunt and then run very close to each other to the input of the isolated modulator; this minimizes the loop area of the connection and reduces the possibility of stray magnetic fields from interfering with the measured signal. If the shunt is not located on the same PC board as the isolated modulator circuit,
a tightly twisted pair of wires can accomplish the same thing. Also, multiple layers of the PC board can be used to increase current carrying capacity. Numerous plated-through vias should surround each non-Kelvin terminal of the shunt to help distribute the current between the layers of the PC board. The PC board should use 2 or 4 oz. copper for the layers, resulting in a current carrying capacity in excess of 20 A. Making the current carrying traces on the PC board fairly large can also improve the shunt's power dissipation capability by acting as a heat sink. Liberal use of vias where the load current enters and exits the PC board is also recommended. Shunt Connections The recommended method for connecting the isolated modulator to the shunt resistor is shown in Figure 21. VIN+ (pin 2 of the HPCL-7860) is connected to the positive terminal of the shunt resistor, while VIN- (pin 3) is shorted to GND1 (pin 4), with the power-supply return path functioning as the sense line to the negative terminal of the current shunt. This allows a single pair of
wires or PC board traces to connect the isolated modulator circuit to the shunt resistor. By referencing the input circuit to the negative side of the sense resistor, any load current induced noise transients on the shunt are seen as a common-mode signal and will not interfere with the current-sense signal. This is important because the large load currents flowing through the motor drive, along with the parasitic inductances inherent in the wiring of the circuit, can generate both noise spikes and offsets that are relatively large compared to the small voltages that are being measured across the current shunt. If the same power supply is used both for the gate drive circuit and for the current sensing circuit, it is very important that the connection from GND1 of the isolated modulator to the sense resistor be the only return path for supply current to the gate drive power supply in order to eliminate potential ground loop problems. The only direct connection between the isolated modulator circuit and the gate drive circuit should be the positive power supply line.
Table 9. Isotek (Isabellenhutte) Four-Terminal Shunt Summary.
Shunt Resistor Part Number PBV-R050-0.5 PBV-R020-0.5 PBV-R010-0.5 PBV-R005-0.5 PBV-R002-0.5 Shunt Resistance m 50 20 10 5 2 Tol. % 0.5 0.5 0.5 0.5 0.5 Maximum RMS Current A 3 7 14 25 [28] 39 [71] Motor Power Range 120 Vac-440 Vac hp kW 0.8-3 0.6-2 2-7 1.4-5 4-14 3-10 7-25 [8-28] 5-19 [6-21] 11-39 [19-71] 8-29 [14-53]
Note: Values in brackets are with a heatsink for the shunt.
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In some applications, however, supply currents flowing through the power-supply return path may cause offset or noise problems. In this case, better performance may be obtained by connecting VIN+ and VIN- directly across the shunt resistor with two conductors, and connecting GND1 to the shunt resistor with a third conductor for the power-supply return path, as shown in Figure 23. When connected this way, both input pins should be bypassed. To minimize electromagnetic interference of the sense signal, all of the conductors (whether two or three are used) connecting the isolated modulator to the sense resistor should be either twisted pair wire or closely spaced traces on a PC board.
The 39 resistor in series with the input lead (R2) forms a lowpass anti-aliasing filter with the 0.01 F input bypass capacitor (C2) with a 400 kHz bandwidth. The resistor performs another important function as well; it dampens any ringing which might be present in the circuit formed by the shunt, the input bypass capacitor, and the inductance of wires or traces connecting the two. Undamped ringing of the input circuit near the input sampling frequency can alias into the baseband producing what might appear to be noise at the output of the device.
FLOATING POSITIVE SUPPLY HV+ GATE DRIVE CIRCUIT
Voltage Sensing The HCPL-7860 Isolated Modulator can also be used to isolate signals with amplitudes larger than its recommended input range with the use of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less than 1 k) so that the input resistance (280 k) and input bias current (1 A) do not affect the accuracy of the measurement. An input bypass capacitor is still required, although the 39 series damping resistor is not (the resistance of the voltage divider provides the same function). The low-pass filter formed by the divider resistance and the input bypass capacitor may limit the achievable bandwidth. To obtain higher bandwidth, the input bypass capacitor (C2) can be reduced, but it should not be reduced much below 1000 pF to maintain adequate input bypassing of the isolated modulator.
R1
D1 5.1 V R2a 39
C1 0.1 F VDD1 VDD2 MCLK MDAT GND2
R2b 39 MOTOR + C2b C2a 0.01 F 0.01 F
VIN+ VINGND1
RSENSE
HCPL-7860
HV-
Figure 23. Schematic for Three Conductor Shunt Connection.
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